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INTEGRATED CIRCUITS 74F299 8-bit universal shift/storage register (3-State) Product specification IC15 Data Handbook 1990 Mar 01 Philips Semiconductors Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 FEATURES * Common parallel I/O for reduced pin count * Additional serial inputs and outputs for expansion * Four operating modes: Shift left, shift right, load and store * 3-State outputs for bus-oriented applications DESCRIPTION The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-Low Master Reset is used to reset the register. The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A Low signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed. A High signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation. PIN CONFIGURATION S0 OE0 OE1 I/O6 I/O4 I/O2 I/O0 Q0 MR 1 2 3 4 5 6 7 8 9 20 VCC 19 S1 18 DS7 17 Q7 16 I/O7 15 I/O5 14 I/O3 13 I/O1 12 CP 11 DS0 GND 10 SF00865 TYPE 74F299 TYPICAL fMAX 115MHz TYPICAL SUPPLY CURRENT (TOTAL) 58mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F299N N74F299D N74F299DB PKG DWG # 20-pin plastic DIP 20-pin plastic SOL 20-pin plastic SSOP II SOT146-1 SOT163-1 SOT339-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DS0 DS7 S0, S1 CP MR OE0, OE1 Q0, Q7 I/On Serial data input for right shift Serial data input for left shift Mode select inputs Clock pulse input (Active rising edge) Asynchronous Master Reset input (Active Low) Output Enable input (Active Low) Serial outputs Multiplexed parallel data inputs or DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 3.5/1.0 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.2mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 70A/0.6mA 3.0mA/24mA 3-State parallel outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High State and 0.6mA in the Low state. 1990 Mar 01 2 853-0365 98989 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 LOGIC SYMBOL 11 18 LOGIC SYMBOL (IEEE/IEC) SRG8 9 2 DS0 DS7 3 1 19 12 11 7 0 1 4R & 3EN13 M 0 3 1 19 12 9 2 3 S0 S1 CP MR OE0 OE1 Q0 I/00 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 C4/1 /2 1, 4D 3, 4D 5, 13 Z5 Z6 8 13 3, 4D 6, 13 6 VCC = Pin 20 GND = Pin 10 8 7 13 6 14 5 15 4 16 17 14 5 15 4 16 18 3, 4D 12, 13 2, 4D Z12 17 SF00866 SF00890 FUNCTION TABLE INPUTS OEn L L L L L H L X = = = = MR L H H H H S1 X H L H L X INPUTS S0 X H H L L X CP X X X OPERATING MODE Asynchronous Reset; Q0 - Q7 = Low Parallel load; I/On Qn (I/On outputs disabled) Shift right; DS0 Q0, Q0 Q1, etc. Shift left; DS7 Q7, Q7 Q6, etc. Hold Outputs in High Z H X High voltage level Low voltage level Don't care Low-to-High clock transition 1990 Mar 01 3 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 LOGIC DIAGRAM DS7 18 OE0 OE1 19 RD 1 2 3 CP D S1 S0 Q 16 I/O7 17 Q7 CP D RD Q 4 I/O6 CP D RD Q 15 I/O5 CP D RD Q 5 I/O4 CP D RD Q 14 I/O3 CP D RD Q 6 I/O2 CP D RD Q 13 I/O1 CP D 11 12 9 RD 8 Q 7 I/O0 DS0 CP VCC = Pin 20 GND = Pin 10 MR Q0 SF00868 1990 Mar 01 4 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IO OUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature Q0, Q7 I/On PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +VCC 40 48 0 to +70 -65 to +150 UNIT V V mA V mA mA C C RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VIH VIL IIK IO OH Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level High level output current Q0, Q7 I/On Low-level Low level output current Operating free-air temperature range Q0, Q7 I/On 0 PARAMETER MIN 4.5 2.0 0.8 -18 -1 -3 20 24 70 LIMITS NOM 5.0 MAX 5.5 V V V mA mA mA mA mA C UNIT IO OL Tamb 1990 Mar 01 5 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONDITIONSNO TAG MIN Q0, Q0 Q7 VO OH High-level High level output voltage I/On VCC = MIN, VIL = MAX MAX, VIH = MIN VCC = MIN, VIL = MAX MAX, VIH = MIN IO = -1mA 1mA OH 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 2.5 2.7 2.4 2.7 3.3 0.35 0.35 -0.73 0.50 0.50 -1.2 100 1 20 -1.2 -0.6 70 3.4 TYP NO TAG UNIT MAX V V V V V V V A mA A mA mA A mA mA mA mA IO = -3mA 3mA OH VO OL VIK II Low-level Low level output voltage Input clamp voltage In ut Input current at maximum input voltage High-level input current Low-level Low level input current Off-state output current, High-level voltage applied Off-state output current Low-level voltage applied others I/On except I/On S0, S1 others IO = MAX OL VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = 5.5V, VI = 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0 5V MAX 0.5V IIH IIL IIH + IOZH IIL + IOZL IOS I/On only VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX -60 55 VCC = MAX 70 -0.6 -150 60 90 Short-circuit output currentNO TAG ICCH ICC Supply current (total) ICCL ICCZ 65 95 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1990 Mar 01 6 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Q0 or Q7 Propagation delay CP to I/On Propagation delay MR to Q0 or Q7 Propagation delay MR to I/On Output Enable time Sn, OE to I/On Output Disable time Sn, OE to I/On I/O Qn Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 Waveform 1 70 85 4.0 4.5 4.0 4.0 5.5 5.5 3.5 4.0 2.5 1.5 TYP 100 115 5.0 6.0 6.0 6.5 7.5 7.5 6.0 7.5 4.5 2.5 7.5 8.0 9.0 9.0 9.5 10.0 8.0 10.0 7.0 5.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 70 85 3.5 4.5 4.0 4.0 5.5 5.5 3.5 4.0 2.5 1.5 8.5 8.5 10.0 10.0 10.5 10.5 9.0 11.0 8.0 6.5 MAX MHz MHz ns ns ns ns ns ns ns ns ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Setup time, High or Low S0 or S1 to CP Hold time, High or Low S0 or S1 to CP Set-up time, High or Low I/On, DSL or DSR to CP Hold time, High or Low I/On, DSL or DSR to CP CP Pulse width, High or Low MR Pulse width, Low Recovery time, MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 6.5 6.5 0 0 3.5 3.5 0 0 5.0 4.5 4.5 4.0 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 7.5 7.5 0 0 4.0 4.0 0 0 5.0 4.5 4.5 4.0 MAX ns ns ns ns ns ns ns ns ns ns ns UNIT 1990 Mar 01 7 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM tW(H) tPHL Q0, Q7, I/On VM tW(L) tPLH tPHL VM Q0, Q7, I/On VM VM CP MR VM tW(L) VM tREC VM SF00869 SF00870 Waveform 1. Propagation Delay, Clock Input to Output, Clock Width, and Maximum Clock Frequency Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time S0, S1, I/On DSL, DSR CP VM ts(H) VM VM th(H) VM ts(L) VM th(L) VM Sn, OEn VM tPZH VM tPHZ VM 0V VOH -0.3V I/On SF00871 SF00872 Waveform 3. Setup and Hold Times Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Sn, OEn VM tPZL VM tPLZ VM VOL +0.3V I/On SF00873 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1990 Mar 01 8 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 TEST CIRCUIT AND WAVEFORM VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V) 90% Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00777 1990 Mar 01 9 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 1990 Mar 01 10 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1990 Mar 01 11 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 1990 Mar 01 12 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 NOTES 1990 Mar 01 13 Philips Semiconductors Product specification 8-bit universal shift/storage register (3-State) 74F299 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05117 Philips Semiconductors yyyy mmm dd 14 |
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